1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus and a manufacturing process therefor.
2. Description of the Related Art
A CMOS-type photoelectric conversion apparatus is widely used as an image pickup element for a digital camera or a digital video camera. In general, the CMOS-type photoelectric conversion apparatus is including a pixel area where pixels including photo diodes (PD) are arranged in a two-dimensional array manner and a peripheral circuit area arranged so as to surround the pixel area.
It is desirably for the CMOS-type photoelectric conversion apparatus to mount a larger number of pixels in a same area along with a recent year's increase in the number of pixels used in the digital camera or the digital video camera, and a size of one pixel in the CMOS-type photoelectric conversion apparatus continuously decreases.
Japanese Patent Laid-Open No. 2003-204055 illustrates a structure of a general CMOS-type photoelectric conversion apparatus. To realize the increase in the number of pixels, wiring layers electrically connecting the respective photo diodes with the transistors have multi-layer interconnection.
Japanese Patent Laid-Open No. 2008-85304 discloses a configuration in which, to secure a sensitivity with respect to incident light even when the pixel scales down, two types of contact structures are provided to an interlayer insulating layer in a wiring section of pixels of the CMOS-type photoelectric conversion apparatus in accordance with a target to be electrically connected. One of the two contact structures is for electrically connecting a semiconductor area with a gate electrode of an amplification MOS transistor without intermediation of the wiring layer. The other contact structure is for electrically connecting an active area and a gate electrode with the wiring layer by stacking a plurality of plugs.
At this point, due to a demand for a higher speed and a higher performance of the photoelectric conversion apparatus, a circuit scale of the entire photoelectric conversion apparatus is being larger. To satisfy this demand, a further miniaturization is required.
According to Japanese Patent Laid-Open No. 2003-204055, two layers of wiring layers including a first wiring layer and a second wiring layer from a side close to the semiconductor substrate, a first interlayer insulating film, and a second interlayer insulating film are provided. Also, in a case where an electric connection is established via two or more layers of interlayer insulating films like a connection from the second wiring layer to the semiconductor substrate, first, the second wiring layer and the first wiring layer are connected to each other via a second via arranged in the second interlayer insulating film. Furthermore, an electric connection between the first wiring layer and the semiconductor substrate is established via a first via arranged in the first interlayer insulating film. With regard to the above-mentioned configuration, the inventors of the present application find the following problem. First, in the above-mentioned configuration, it is necessary to secure an area for forming the first wiring layer used for connecting the first via with the second via, and it is difficult to realize the miniaturization of the first wiring layer. Also, for example, in a floating diffusion section of the CMOS type photoelectric conversion apparatus, in a case where the area of an opposing metal wiring is large, an electrostatic capacity between the floating diffusion section and the metal wiring becomes large. The problem of the increase in the electrostatic capacity has a larger influence as the miniaturization further advances because a distance between the floating diffusion section and the metal wiring is shortened. The above-mentioned increase in the capacitance of the floating diffusion section may cause a decrease in the signal charges generated through the photoelectric conversion.